This invention relates to a memory test pattern generator for generating a test pattern for a so-called nibble memory, which has internal address generating means and is capable of address accessing by merely supplying a clock signal.
A semiconductor random access memory (hereinafter referred to as RAM) is capable of random access to all the addresses. All the addresses are accessed by an externally supplied address signal.
There is one kind of RAM called nibble memory, which has internal address generating means and is capable of incrementing internal address by merely supplying a clock signal. An example of this memory is "MB81257" by Fujitsu Co., Ltd. in Japan. This memory is capable of freely accessing all the addresses in the normal mode like the ordinary memory. The nibble memory can operate in a nibble mode, i.e., internal address mode as well as in the normal mode. In the internal address mode, the following operation takes place. When the internal address mode is set with one of the addresses of the memory accessed, several, usually three, addresses following the accessed address can also be accessed by merely supplying a clock signal. The memory has a small internal address counter (address generation means) for generating internal addresses each constituted by, for example, two bits in the case of the nibble mode. The counter is incremented from a count corresponding to the last externally accessed address. A typical nibble memory has a two-bit internal counter and is capable of address increments for three addresses. It is possible to set a desired number of increments, for instance corresponding to one page, achieving a page mode. The maximum number of increments is determined by the modulo of the address counter provided in the memory. For this reason, in a broad sense, the nibble mode operation can be regarded as the internal address operation. In the internal address operation (or mode), high speed reading and writing of data can be realized compared to the case where the addresses are accessed one by one under control of an externally supplied address signal.
FIG. 1 shows operational waveforms illustrating the internal address mode.
A row address X (shown in row C of FIG. 1) is written in the memory with the fall of a row address strobe signal RAS (shown in row A of FIG. 1), and subsequently a column address Y (shown in row C of FIG. 1) is written in the memory with the fall of a column address strobe signal CAS (shown in row B of FIG. 1). In this way, an address of the memory is accessed. This accessing operation is the same as in the normal mode. Data D1 (as shown in row D of FIG. 1) is read out from or written in synchronization with operation clocks M in the address determined by the selected row and column addresses X and Y.
In the internal address mode, the column address strobe signal CAS is alternately and repeatedly changed to H and L levels (as shown in row B of FIG. 1) while holding the row address strobe signal RAS at L level (as shown in row A of FIG. 1). The column address strobe signal CAS at this time serves as a clock signal. The internal address counter (i.e., internal address generation means) in the memory is incremented or decremented at every fall of the signal. Thus, three addresses following the address specified by the address (X, Y) are accessed, and data D2 to D4 are read out or written in. The period MN before the start of the internal address mode, each access period NN in the internal address mode and the period NM after the end of the internal address mode are referred to as nibble-in cycle, nibble cycle and nibble-out cycle, respectively, and are related as MN&gt;NM&gt;NN.
In the operation of reading or writing data D1 in the normal mode, the strobe signals RAS and CAS are caused to fall to latch the row and column addresses and, after writing or reading data, to rise to prepare for the next access cycle in a predetermined sequence. In this case, one access operation cycle requires a time MN+NM. Therefore, if these data D1 to D4 are written in or read out in the normal mode, a time period of 4(MN+NM) is required. Thus, the speed of writing or reading data D1 to D4 in the internal address mode is higher than the speed in the normal mode.
The memory tester usually has a construction as shown in FIG. 2. A pattern generator 11 successively supplies test patterns to a device under test (DUT) 13 and also supplies expected value patterns DS to a comparator 14. The test patterns to be supplied to the DUT 13, i.e., addresses and, if necessary, write data DW are shaped in a shaper 12 so as to have various desired waveforms, timings and levels before being supplied to the DUT 13.
The write data DW is written in the DUT 13, and also a read data pattern DR is read out from the DUT 13 and supplied to the comparator 14. The comparator 14 checks whether the read-out data pattern DR coincides with a correct pattern, i.e., the expected value pattern DS. If the two patterns fail to coincide with each other, a signal representing failure, is written into the corresponding address of a fail memory 15. The pattern generator 11 includes a microinstruction program memory 1 having an instruction code area 1A, an address operation instruction area 1B, a data operation instruction area 1C and a timing data area 1D, all of which are simultaneously accessed with an address specified by the program counter 2. A timing pulse generator 16 receives timing data from the timing data area 1D, and according to the received timing data it produces various timing pulses for controlling the timing of advancing the program counter 2, timing of reading and writing data in and out of the DUT 13, timing of comparison operation of the comparator 14, timing of writing in the fail memory 15, etc.
The pattern generator 11 includes the program counter 2, which supplies an access address to the memory 1, a program counter controller 3, an address generator 4 and a data generator 5 in addition to the microinstruction program memory 1. When the address of the program counter 2 is supplied to the microinstruction program memory 1 so that the memory address is accessed, instructions are read out from the various areas in the program memory 1. The program counter 2 is incremented or decremented every time an instruction is read out from the program memory 1. Also, it receives a jump control by the program counter controller 3 according to an instruction code read out from the instruction code area 1A. The address generator 4 operates to generate an address pattern in accordance with an address operation instruction read out from the address operation instruction area 1B. The data generator 5 produces data patterns, i.e., the write data DW and expected value data DS, according to data operation instruction read out from the data operation instruction area 1C.
The address data and write data DW provided from the address and data generators 4 and 5, respectively, are supplied to the shaper 12 to be shaped into a selected one of various waveforms for being supplied to the DUT 13 under control of a timing signal from the timing pulse generator 16. The DUT 13 is accessed by the addresses supplied from the address generator 4 for writing and reading data under control of respective write and read pulses supplied from the timing signal generator 16. The read data pattern DR read out from the DUT 13 is supplied to the comparator 14 to be compared to the expected value pattern DS from the data generator 5. If the two compared patterns fail to coincide with each other, a signal representing the failure is written in the same address of the fail memory 15 as the address for the DUT.
The operation explained so far is the same as the usual memory test operation. Now, a test of a memory with an internal address function will be described. As mentioned before, the memory with the internal address function has an internal address generation means, which is caused to generate internal addresses by supplying a clock signal such as to cause alternate and repeated inversion of the row strobe signal RAS to H and L levels while holding an externally applied address unchanged. The internal addresses are successively substituted for predetermined bits of the externally supplied address, whereby high speed address accessing is effected without incrementing the externally supplied address.
In the tester, the same addresses as those internally generated in the DUT 13 have to be generated because it is necessary to identify the address of the DUT 13, from which data is being read out. That is, the same address as that internally generated in the DUT 13 also has to be externally generated for comparison and accessing to the fail memory 15.
Heretofore, operation instructions for generating the same addresses as internal addresses are written in the address operation instruction area 1B, and the same addresses as the internal addresses to be accessed are generated in the periods MN, NN and NM of the internal address mode according to the operation instructions. For example, in order to operate the DUT in a nibble mode starting with an address composed of column and row addresses X and Y, it has been necessary, in the prior art, to prepare and write in the microinstruction program memory 1 a microinstruction program as shown in FIG. 3 for the testing of the DUT 13 in the internal address mode with respect to the address (X, Y). Let it be supposed that the internal address (e.g. column address) is incremented by one, three times to produce four internal addresses, the LSB of the write data DW having been generated from the data generator 5 immediately before entering the internal address mode is "0", and new write data "1", "1", "0" and "1" are to be written in these four addresses in the mentioned order. Also, it is supposed that the timing data TS0 prior to the internal address generation, that is, the nibble-in cycle data is set to TS0=100 nsec., the timing data TS1 during each internal address generation, that is, the nibble cycle data is set to TS1=29 nsec., and the timing data TS2 subsequent to the internal address generation, that is, the nibble-out cycle data is set to TS2=50 nsec.
As shown in FIG. 3, all the instruction codes in first to fourth steps (1) to (4) in the internal address mode are NOP instructions. The address operation instruction is as follows. In the first step (1), the column address X is incremented by 1, while the row address Y is incremented by 1 only if there is a carry from X, reaching the start address of the internal address mode. The internal address N of the DUT 13 is set to an initial internal address, e.g. "0,0" which is given by predetermined bits of the start address. In each of the second to fourth steps (2) to (4), the internal address N of the DUT 13 is incremented by 1 according to the column address strobe CAS (i.e., operation clock), i.e., every time data is written in the DUT 13. While, a value N in an internal register (not shown) of the address generator 4 is set to the same value as the initial internal value "0,0", and thereafter the content of the internal register is renewed as expressed by N.rarw.N+1 in each of the steps (2) to (4). In each of the steps (1) to (4), the value N of the internal register and the start address are combined to produce an address. In this way, the same address as the internally generated address of the DUT 13 is obtained from the address generator 4 and supplied to the fail memory 15.
As mentioned before, the least significant bit of the write data immediately before entering the internal address mode is "0", and data "1", "1", "0" and "1" are to be written in the respective first to fourth steps in the internal address mode. Therefore, the instructions in the data operation instruction area 1C are as shown in column 1C in FIG. 3. Here, /D signifies that the input data is provided after being inverted. Since the immediately preceding input data is "0", operation instructions as shown in column 1C of FIG. 3 are obtained. In the first to fourth steps, respective instructions TS0 to TS2 as shown in FIG. 3 are written in the timing data area 1D, according to which timing data 100, 20, 20 and 50 nsec. are obtained in the steps (1) to (4).
In the prior art, even in the internal address mode, data is read out from the microinstruction program memory 1 for each internal address generation. This means that it is necessary to produce a microinstruction such as to obtain a desired operation for each internal address generation. This operation is comparatively time-consuming. In addition, since a microinstruction program is produced for every step, considerable time is required for the debugging, i.e., checking as to whether there is no error in the program and correcting an error if any. Further, the microinstruction program memory 1 should have a comparatively large capacity. Furthermore, the significance of the above problems is increased with increase of the steps (internal addresses) in the internal address mode.